1. Field of the Invention
The present invention generally relates to the formation of integrated circuit components and, more particularly, to capacitors suitable for use in high capacity memory devices and other components which may benefit from elements formed at sub-lithography dimensions.
2. Description of the Prior Art
A principal component of all digital data processing systems is a random access memory (RAM) device. Many designs for random access memory devices are known which rely on the storage of charge in a capacitor to reflect the logic states of bits of data or instructions. Such designs are generally referred to as dynamic random access memories (DRAMs) since they must be periodically refreshed to compensate for loss of stored charge. For extreme high speed operation, high density of integration of storage cells is of paramount importance to achieve high storage capacity. At the same time, however, each memory cell must store the largest amount of charge possible, consistent with integration density in order to avoid frequently rewriting of the memory.
As is well-known, the amount of charge which can be stored at a given voltage decreases with the area of capacitor plates which can be provided. It is desirable to store as much charge as possible since all capacitor structures are subject to loss of charge through leakage and other effects. However, as integration densities have increased, the amount of space available on a chip for formation of the capacitor plates has become increasingly limited.
For this reason and because it is similarly well-known that charge storage capability can be increased with decrease in spacing between the capacitor plates and increase of the dielectric constant of insulator material placed between the plates, various geometries of so-called vertical stack capacitors have been developed in order to provide additional plate area with very thin dielectric layers between the plates within a given "foot print" on the chip. However, designs of vertical stack capacitors have been limited by the resolution of lithographic processes used to define and achieve these geometries. Therefore, the practical limits of lithography processes has been a problem in development of designs for memories having greater than 64 Mb on a single chip, even though materials of high dielectric constant have been recently developed.
Additionally, to develop complex geometries to increase capacitor plate surface area for memory cells, the number of process steps must be greatly increased. Since each step of the fabrication of semiconductor devices may be imperfectly performed, the manufacturing yield of such devices generally decreases as the number of manufacturing steps is increased.
This is also true for manufacturing steps which are used to develop surface characteristics such as hemispherical grain, rough polysilicon and the like which can significantly increase effective capacitor plate surface area and which are often collectively referred to as random surface technologies. Such random surface technologies have been virtually the only recourse to increase capacitor plate surface area for a particular lithographic resolution or minimum feature size of design rules consistent with a particular footprint area of the capacitor. While surface area can often be increased by a factor of up to about 1.5-2.0, control of the formation of such surfaces often increases the variation in capacitance between memory cells on the same chip and from chip to chip.
While the ability to store increased amount of charge in a capacitor of a limited size is especially critical in memory devices, due to the number of capacitors which may be required on a single chip, many other applications requiring capacitors and other elements in integrated circuits (e.g. isolation structures) are known which have also been limited in size and, often, in structural integrity by the resolution of the exposure tool used in lithographic processes. Therefore, a need has existed in the art for a process which is capable of forming circuit element features at smaller sizes than can be produced from particular lithographic exposure tools.